Detailed-Routability of FPGAs with Extremal Switch-Block Structures

Authors:
Y. Takashima;A. Takahashi;Y. Kajitani
Affiliations:
Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech., 2-12-l Ookayama, Meguro-ku, Tokyo 152, Japan;Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech., 2-12-l Ookayama, Meguro-ku, Tokyo 152, Japan;Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech., 2-12-l Ookayama, Meguro-ku, Tokyo 152, Japan
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 2
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Abstract

The architecture of FPGAs is discussed to see trade-offs between programmable-switch resources in switch-blocks and detailed-routability. For the purpose, FPGAs are assumed to have certain extremal structures. A polynomial time detailed-routing for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. While, the corresponding decision problem is proved to be NP-complete for other FPGAs. A best compromise between switch resources and detailed-routability is offered.