Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Performance evaluation of an event-driven logic simulation machine
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
VHDL, Hardware Description and Design
VHDL, Hardware Description and Design
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Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation by parallel processing. We developed the method to extract parallelism from behavioral descriptions for fast simulation utilizing these machines. We evaluated our methods utilizing CAD accelerator TP5000. By the extraction of the parallelism the simulation speed is accelerated about 7 times.