Low power FSM design using Huffman-style encoding

  • Authors:
  • P. Surti;L. F. Chao;A. Tyagi

  • Affiliations:
  • Intel Corporation, Folsom, California;Iowa State University, Ames, Iowa;Iowa State University, Ames, Iowa

  • Venue:
  • EDTC '97 Proceedings of the 1997 European conference on Design and Test
  • Year:
  • 1997

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Abstract

This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.