Self recovering controller and datapath codesign
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Efficient Self-Recovering ASIC Design
IEEE Design & Test
An error recoverable structure based on complementary logic and alternating-retry
Journal of Computer Science and Technology
Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints
Journal of Signal Processing Systems
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In this paper, we have developed a methodology for behavioral synthesis of an important class of reconfigurable data path designs called configurable spare processors. Traditionally, a processor failure has been tolerated by dedicating a spare for the processor. However, this has a significant area overhead. In contrast, we present a new technique wherein several processors share one or more configurable spare processors. A configurable spare efficiently implements any of k applications and can be configured to substitute for a faulty processor implementing one of these k applications. In this paper, we address three important techniques targeting configurable spare processor synthesis. Firstly, we address application bundling wherein n application control-data flow graphs (CDFGs) are bundled into at most m groups such that the sum of the areas of the corresponding implementations is minimized. All throughput and fault-tolerance constraints for all applications are satisfied. The area overhead of each of the application bundles is further optimized by retiming the applications within a bundle} by considering its effects on the remaining applications in the bundle. Finally, each application bundle is synthesized into a configurable spare processor. The effectiveness of all approaches, algorithms, and software implementations is demonstrated on a number of real-life examples. The validation of all presented examples is complete in a sense that we conducted functional simulation to complete layout implementations.