Architecture Design of a Scalable Single-Chip Multi-Processor

  • Authors:

  • B. D. Theelen;A. C. Verschueren

  • Affiliations:

  • -;-

  • Venue:
  • DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
  • Year:
  • 2002

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Abstract

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture [1]. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MµP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we explore the main design issues of the architecture platform on which the MµP is based.