A VLSI chip for computing the medial axis transform of an image

Authors:
N. Ranganathan;K. B. Doreswamy;V. Cantoni;L. Lombardi;M. Mosconi;M. Savini;A. Setti
Affiliations:
-;-;-;-;-;-;-
Venue:
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
Year:
1995

Citing 0
Cited 3

Design of a Cellular Architecture for Fast Computation of the Skeleton

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Parallel implementation of exact dilations and multi-scale skeletonization

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Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

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Abstract

We describe a new special purpose VLSI architecture for computing the medial axis transform of an image. The architecture is systolic and is based on an algorithm that achieves a high degree of parallelism. The proposed algorithm computes the skeleton of multiple objects in an image in linear time by making 2 scans over the 4 distance transform of the image. The algorithm is mapped onto a linear systolic array of simple processing elements (PEs) and for an N/spl times/N image, the architecture requires N PE's. The entire array can be realized in a single VLSI chip. The proposed hardware can perform thinning on a 512/spl times/512 image in 2.59 msec and on a 256/spl times/256 image in 0.327 msec. A prototype CMOS VLSI chip implementing the proposed architecture has been designed and verified.