Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
VirtualClock: a new traffic control algorithm for packet-switched networks
ACM Transactions on Computer Systems (TOCS)
SIGCOMM '92 Conference proceedings on Communications architectures & protocols
An efficient rate allocation algorithm for ATM networks providing max-min fairness
Proceedings of the IFIP Sixth International Conference on High Performance Networking VI
Providing bandwidth guarantees in an input-buffered crossbar switch
INFOCOM '95 Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 3)-Volume - Volume 3
FRAME-BASED FAIR QUEUEING: A NEW TRAFFIC SCHEDULING ALGORITHM FOR PACKET-SWITCHED NETWORKS
FRAME-BASED FAIR QUEUEING: A NEW TRAFFIC SCHEDULING ALGORITHM FOR PACKET-SWITCHED NETWORKS
FAST: AN FPGA-BASED SIMULATION TESTBED FOR ATM NETWORKS
FAST: AN FPGA-BASED SIMULATION TESTBED FOR ATM NETWORKS
CPU design kit: an instructional prototyping platform for teaching processor design
WCAE '95 Proceedings of the 1995 workshop on Computer architecture education
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Efficient fair queueing algorithms for packet-switched networks
IEEE/ACM Transactions on Networking (TON)
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Simulation of ATM switches and networks is a computationally demanding problem as compared to simulation of conventional packet-based networks, owing to the large number of cell events that need to be simulated in the former. To address this problem, we are developing a flexible hardware simulation testbed in the High-Speed Networks Laboratory at the University of California, Santa Cruz. The testbed, called FAST (FPGA-based ATM simulation testbed), uses high-density field-programmable gate arrays (FPGAs) to allow implementation of the key simulation components such as traffic generators, switching fabric, buffer management, traffic scheduling, congestion control mechanisms, and statistics recording in hardware. In the first version of the testbed (FAST-1), each board consists of 13 Altera FLEX devices (including 4 multichip modules), providing a total of 336,000 usable gates. Each board can be used to simulate an ATM switch. Multiple boards may be interconnected to simulate large ATM networks. Software tools are being developed for specifying the components of the underlying simulation model, such as the switch structure, traffic arrival process, traffic scheduling algorithm, and congestion control algorithm; synthesizing the specifications into the individual FPGAs; controlling and monitoring the simulation; and collecting and reporting statistics. The paper provides an overview of the architecture of the FAST-1 board, describes its key components, and discusses an example simulation of a traffic scheduling algorithm using the board.