A Statistically Rigorous Approach for Improving Simulation Methodology
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor
IEEE Transactions on Computers
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices
APPT '09 Proceedings of the 8th International Symposium on Advanced Parallel Processing Technologies
Algorithms and architectures for 2D discrete wavelet transform
The Journal of Supercomputing
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The internal architecture of a 2000 MIPS/1000 MFLOPS (peak) high-performance low cost CMOS Alpha micro-processor chip is described. This implementation is derived from the Alpha 21164 microprocessor to reduce cost while maintaining high performance. It contains a quad-issue super-scalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit have been re-designed to provide a high performance memory system using industry standard PC SRAM and DRAM components.