Exploiting Program Branch Probabilities in Hardware Compilation
IEEE Transactions on Computers
| Hi-index | 0.00 |
We describe a feasibility study into accelerating computer graphics radiosity calculations using reconfigurable hardware. A modular hardware/software codesign framework has been developed for experimenting with hardware acceleration of a time consuming step: form factor determination. We describe a parameterised hardware design pattern, captured in the Handel-C language, which enables rapid exploration of the area/throughput design space for simple pipelines. Using this pattern we determine speedup and resource usage on a range of Xilinx Virtex FPGA devices, and examine future trends in performance. As a sample of these results we demonstrate a 7.6 times speed-up over a 1.4GHz Athlon PC using a Xilinx XCV2000E and, based on place and route reports, estimate 31 times speedup using a XilinxXC2V8000.