64-bit floating-point FPGA matrix multiplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Automatic application specific floating-point unit generation
Proceedings of the conference on Design, automation and test in Europe
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of reconfigurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost function with a given error specification for the output relative to a reference representation can be satisfied. Currently our tool, which adopts an iterative implementation of this method, supports single- or double-precision floating-point representation as the reference representation. It produces customised floating-point formats with arbitrary-sized mantissa and exponent. Results show that, for calculations involving large dynamic ranges, our method can achieve significanthardware reduction and speed improvement with respect to a design adopting the reference representation.