Enabling technologies for petaflops computing
Enabling technologies for petaflops computing
Polling watchdog: combining polling and interrupts for efficient message handling
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
A study of the EARTH-MANNA multithreaded system
International Journal of Parallel Programming - Special issue on parallel architectures and compilation techniques—part II
Costs and Benefits of Multithreading with Off-the-Shelf RISC Processors
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
A Parallel-Object Programming Model for PetaFLOPS Machines and Blue Gene/Cyclops
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Next Generation System Software for Future High-End Computing Systems
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
COOL Approach to Petaflops Computing (invited paper)
PaCT '999 Proceedings of the 5th International Conference on Parallel Computing Technologies
A Scalable Interconnection Network Architecture for Petaflops Computing
The Journal of Supercomputing
Languages and Compilers for Parallel Computing
Single-particle 3d reconstruction from cryo-electron microscopy images on GPU
Proceedings of the 23rd international conference on Supercomputing
Enhanced loop coalescing: a compiler technique for transforming non-uniform iteration spaces
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Effective out-of-core parallel delaunay mesh refinement using off-the-shelf software
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Analysis and performance results of computing betweenness centrality on IBM Cyclops64
The Journal of Supercomputing
| Hi-index | 0.00 |
The objective of the hybrid technology multithreaded architecture (HTMT) research is to determine the feasibility and structure of a parallel architecture integrating the combined capabilities of semiconductor, superconductor, and optical technologies. This mix of technologies may yield operational attributes superior to those based solely on semiconductor technology. The authors present a brief overview of the crucial technology-the superconducting rapid single-flux quantum logic (RSFQ) technology, as well as the HTMT multithreaded program execution models and architecture. The HTMT approach exploits key emerging devices. Specifically, computational performance can be dramatically improved through recent advances in RSFQ technology, making 100 GHz clock rates feasible in the near future. Memory capacity may be drastically increased through a new memory hierarchy merging superconductor memory, advanced semiconductor high-density memory and future optical 3D holographic storage. Interconnection bandwidth will be greatly enhanced by means of optical networks with very high bandwidth.