Parallel VLSI Architectures for Cryptographic Systems

  • Authors:
  • Fabio Ancona;Alessandro de Gloria;Rodolfo Zunino

  • Affiliations:
  • -;-;-

  • Venue:
  • GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
  • Year:
  • 1997

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Abstract

This paper describes a parallel VLSI implementation of a private-key cryptographic system based on Peano- Hilbert curves. The basic unit of the VLSI architecture is the Crypto Processor, that is an SIMD composed of a grid of 256x256 processing units performing elementary operations of encoding process. The key length of the system, measured as number of free parameters, depends linearly on hardware complexity: the cryptographic system is modular and its implementation is very cheap. The CP has been implemented as a single chip with a 1-micron CMOS technology and shows a working frequency of 30 MHz. The chip can be used in consumer applications as well as add-on whenever a certain degree of safety in communication is required.