Iterative layering: optimizing arithmetic circuits by structuring the information flow
Proceedings of the 2009 International Conference on Computer-Aided Design
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This paper presents a methodology for delay estimation of hardware components described at the behavioral-level. The basis of the proposed technique is a well-known theoretical result that relates the entropy of a logic function to the delay of a multi-level implementation of the same function. We propose an improved model for delay estimation, and we prove its validity by means of experiments performed on a set of standard benchmarks.