Bus minimization and scheduling of multi-chip systems

  • Authors:

  • M. Sheliga;E. Hsing-Mean Sha

  • Affiliations:

  • -;-

  • Venue:
  • GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
  • Year:
  • 1995

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Abstract

This paper considers several different algorithms that reduce the required number of buses for multi-chip module design. An efficient polynomial time algorithm that calculates the minimum number of buses needed given a particular schedule is presented. We also present three algorithms that minimize the number of buses during scheduling. Experimental results are shown that illustrate the efficiency of the algorithms.