Routing method for VLSI design using irregular cells
DAC '83 Proceedings of the 20th Design Automation Conference
Placement and routing algorithms for hierarchical integrated circuit layout
Placement and routing algorithms for hierarchical integrated circuit layout
Shape determination and placement algorithms for hierarchical integrated circuit layout
Shape determination and placement algorithms for hierarchical integrated circuit layout
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Module placement on BSG-structure and IC layout applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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A completely hierarchical approach to integrated circuit design begins by partitioning a design problem into subproblems which are based on functional boundaries. It is desirable to produce a final layout which is compact, yet preserves the functional decomposition. Allowing the physical macrocells to have arbitrary rectilinear shapes permits this goal to be achieved but introduces many levels of complexity into the modeling of the assembly. To support macrocells with rectilinear shapes, a directed graph, referred to as an adjacency graph is used to model the positional relationship of the components in the assembly. Algorithms are presented for constructing the adjacency graphs, identifying the cycles present in the adjacency graph, converting the graph to an acyclic graph, and for establishing the component and channel positions based on a critical path analysis. These algorithms are implemented in Pascal on a DECSYSTEM-20.