The sociology of microprogramming
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Virtualizing the VAX architecture
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
IEEE Transactions on Computers
Naming and Binding in a Vertical Migration Environment
IEEE Transactions on Software Engineering
Migration implementation by integrating microprogramming and HLL programming
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
An automatic migration scheme based on modular microcode and structured firmware sequencing
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Toward type-oriented dynamic vertical migration
ACM SIGMICRO Newsletter
Performance and security lessons learned from virtualizing the alpha processor
Proceedings of the 34th annual international symposium on Computer architecture
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The concepts and theory behind a specific type of hardware accelerator, oar “assist”, are presented. Such accelerators are specific extensions to an existing, generalized data processor architecture. Both the software system and the hardware implementation are changed by the extensions. For the accelerators discussed here, the hardware implementation is accomplished solely in microcode. The generalized architecture can be compatible across a line of data processors. The accelerators are defacto extensions to the basic architecture and are normally only defined on a subset of the processor line. These architectural extensions consist of functions migrated from “above” the generalized architecture (i.e. software functions) into the processor architecture and processor implementation. The accelerators provide a method of improving system performance that is complementary to improving performance through modification of the generalized processor architecture itself or the underlying circuitry implementation.