A pedagogical processor model

Authors:
Will D. Gillett;Eric B. Muehrcke
Affiliations:
Department of Computer Science, Washington University, Box 1045, St. Louis Mo.;Department of Computer Science, Washington University, Box 1045, St. Louis Mo.
Venue:
SIGCSE '83 Proceedings of the fourteenth SIGCSE technical symposium on Computer science education
Year:
1983

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Abstract

This paper presents a pedagogical processor model, intended for teaching fundamental concepts about von Neumann machines. A general discussion of the desirable pedagogical properties is given, and a specific one address machine is defined. The machine has a simple architecture, supports four addressing modes, and uses a small number of hierarchically organized, fixed-field instructions. Debugging capabilities are included in the definition and can be accessed by executable instruction.