The Piecewise Data Flow architecture control flow and register management

Authors:
Joseph E. Requa
Affiliations:
-
Venue:
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Year:
1983

Citing 3
Cited 2

The CRAY-1 computer system

Communications of the ACM - Special issue on computer architecture
The Theory of Parsing, Translation, and Compiling

The Theory of Parsing, Translation, and Compiling
The Piecewise Data Flow Architecture: Architectural Concepts

IEEE Transactions on Computers

Asynchrony in parallel computing: from dataflow to multithreading

Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading

Progress in computer research

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the hardware register management and instruction block control flow sequencing provided by the PDF block processing section of the Piecewise Data Flow machine, a proposed high performance computer architecture. Combined, these capabilities provide the maximum allowed execution overlap of instruction blocks with minimum hardware contention and high hardware utilization.