µ3L: An HLL-RISC processor for parallel execution of FP-language programs

Authors:
M. Castan;E. I. Organick
Affiliations:
Department of Computer Science, University of Utah, Salt Lake City, Utah;Department of Computer Science, University of Utah, Salt Lake City, Utah
Venue:
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Year:
1982

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Abstract

To eliminate the conceptual distance between the hardware instruction set and the user interface, some architects advocate High Level Language (HLL) machines. To obtain simple, fast and cheap machines, some architects advocate Reduced Instruction Set Computer (RISC) machines. This paper reconciles both views and presents an architecture which has both an HLL user interface and a RISC hardware. Each instance of this architecture is a module of an HLL multiprocessor system. Functional programming languages offer a bridge between mathematical models of computation and multiprocessor system environments. We choose the language AFPL (A Functional Programming Language) as the HLL user interface. AFPL's direct execution model, based on a tree structured internal representation, takes advantage of the parallelism inherent in programs by decomposing them on the fly into tasks which can be performed concurrently.