Open, Closed, and Mixed Networks of Queues with Different Classes of Customers
Journal of the ACM (JACM)
Multiprocessor Organization—a Survey
ACM Computing Surveys (CSUR)
Communications of the ACM - Special issue on computer architecture
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
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We propose a multitrack bus architecture: a novel interconnection scheme of functional units in a multiprocessor system. It features concurrent data transfer among functional units and flexible bus structure. We have clarified the possibility of more mass transfer of data in comparison with conventional interconnection schemes.