A virtual memory for microprocessors
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Operating systems
| Hi-index | 0.00 |
This paper presents a virtual memory system which may be connected to the memory bus of a host computer. The system is based on the use of a separate processor to interface to the backing store and perform all the processing related to managing the virtual memory. The proposed approach provides a virtual memory that is transparent to the host processor, with one exception. When a memory reference generated by the host results in a page fault, a long delay is encountered. This delay corresponds to the time taken by the virtual memory controller to carry out a page transfer. A prototype system based on the above approach has been constructed. Bubble memory devices are used to implement the backing store. The suitability of bubble memories in this environment is discussed in the paper.