Evaluation methods in SARA—the graph model simulator

  • Authors:

  • Rami R. Razouk;Mary Vernon;Gerald Estrin

  • Affiliations:

  • Computer Science Department, University of California, Los Angeles, California;Computer Science Department, University of California, Los Angeles, California;Computer Science Department, University of California, Los Angeles, California

  • Venue:
  • SIGMETRICS '79 Proceedings of the 1979 ACM SIGMETRICS conference on Simulation, measurement and modeling of computer systems
  • Year:
  • 1979

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Abstract

The supported methodology evolving in the SARA (System ARchitects' Apprentice) system creates a design frame-work on which increasingly powerful analytical tools are to be grafted. Control flow analyses and program verification tools have shown promise. However, in the realm of the complex systems which interest us there is a great deal of research and development to be done before we can count on the use of such powerful tools. We must always be prepared to resort to experiments for evaluation of proposed designs. This paper describes a fundamental SARA tool, the graph model simulator. During top-down refinement of a design, the simulator is used to test consistency between the levels of abstraction. During composition, known building blocks are linked together and the composite graph model is tested relative to the lowest top-down model. Design of test environments is integrated with the multilevel design process. The SARA methodology is exemplified through design of a higher level building block to do a simple FFT.