The design of a system for the synthesis of correct microprograms
MICRO 8 Proceedings of the 8th annual workshop on Microprogramming
Modeling for synthesis - the gap between intent and behavior
Proceedings of the Symposium on Design Automation and Microprocessors
Proceedings of the Symposium on Design Automation and Microprocessors
The graph model of behavior simulator
Proceedings of the Symposium on Design Automation and Microprocessors
Specialization of SARA for software synthesis
Proceedings of the Symposium on Design Automation and Microprocessors
Automatic generation of assemblers.
Automatic generation of assemblers.
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Modeling for synthesis - the gap between intent and behavior
Proceedings of the Symposium on Design Automation and Microprocessors
The graph model of behavior simulator
Proceedings of the Symposium on Design Automation and Microprocessors
Specialization of SARA for software synthesis
Proceedings of the Symposium on Design Automation and Microprocessors
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This paper concerns itself with issues in development of building blocks for use in structured synthesis of computer systems and bases its discussion on experiences with behavioral modelling of the 8080 microprocessor. The SARA (System ARchitects Apprentice) system offers a set of modelling and analysis tools intended to aid a designer in a structured design procedure [EST77, GAR77, RAZ77, CAM77, GAR75, FEN76]. Every design developed with the help of SARA terminates in a composition (bottom-up) step in which previously validated models of elements (building blocks) are joined together. The multi-level modelling which SARA is supposed to support [GAR77] depends upon the fact that building block models use the same primitives as higher level systems. This paper discusses experiments with development of machine processable models using graph model primitives for the 8080 family via the SARA tools.