A universal interconnection pattern for parallel computers
Journal of the ACM (JACM)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Bounds on the time for parallel RAM's to compute simple functions
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
New lower bounds for parallel computation
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
One, two, three . . . infinity: lower bounds for parallel computation
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Are search and decision programs computationally equivalent?
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
New lower bounds for parallel computation
Journal of the ACM (JACM)
Parallel RAMs with bounded memory wordsize
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
A lower bound for parallel string matching
STOC '91 Proceedings of the twenty-third annual ACM symposium on Theory of computing
ACM SIGARCH Computer Architecture News
A constant-time optimal parallel string-matching algorithm
STOC '92 Proceedings of the twenty-fourth annual ACM symposium on Theory of computing
A constant-time optimal parallel string-matching algorithm
Journal of the ACM (JACM)
Incomparability in parallel computation
SFCS '87 Proceedings of the 28th Annual Symposium on Foundations of Computer Science
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Shared-memory models for parallel computation (e.g. parallel RAMs) are very natural and already widely used for parallel algorithm design. The various models differ from each other mainly in the way they restrict simultaneous processor access to a shared memory cell. Understanding the relative power of these models is important for understanding the power of parallel computation. Two recent pioneering works shed some light in this question. Cook and Dwork [CD] (resp. Snir [S]) present problems that, for instances of size n, can be solved in O(1) time on an n-processor PRAM that allows simultaneous write (resp. read) access to shared memory, but require &Ohgr;(log n) time on a PRAM that forbids simultaneous write (resp. read) access, regardless of the number of processors. When allowing simultaneous write access, the model must include a write-conflict resolution scheme. Three such schemes were suggested in the literature, and in this paper we study their relative power. Here the situation is more sensitive, as a small increase in the number of processors allows constant time simulation of the strongest by the weakest. By fixing the number of processors and parametrizing the number of shared memory cells, we obtain tight separation results between the models, thereby partially answering open questions of Vishkin [V]. New lower bounds techniques are developed for this purpose.