Simulation of structured hardware designs

  • Authors:
  • Charles M. Shub

  • Affiliations:
  • -

  • Venue:
  • WSC '80 Proceedings of the 12th conference on Winter simulation
  • Year:
  • 1980

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Abstract

The need for simulating structured hardware designs at the clock pulse level is described. The conceptual components of such a simulator are delineated both for the Algorithmic State Machine which controls the hardware and the hardware components which are controlled. The minimal design restrictions which are made are justified not only in terms of practicality and simplification of the simulator, but also in terms of good structured design practice. The concepts are extended to multiple parallel controllers and loosely coupled controllees. Several examples of simulating a simple hardware design which plays blackjack are presented. Preliminary results and trends in the simulation of a parallel architecture LISP machine are also delineated. Suggestions are made for further improvements and enhancements.