A loop network for simultaneous transmission of variable-length messages
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Design and simulation of the distributed loop computer network (DLCN)
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Techniques: Survey of computer communications loop networks: Part 1
Computer Communications
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This paper reports the results of a performance study of an experimental computer communication network. The network is currently being designed and built in order to test concepts and techniques that may find future application. The network consists of synchronous digital transmission lines connected in loops to a Central Switch. User traffic enters the system through multiplexers connected to the synchronous lines. The Central Switch has the two-fold function of routing and controlling traffic. Two multiplexing techniques were examined, Demand Multiplexing (DM) and Synchronous Time Division Multiplexing (STDM). In both techniques user messages are blocked into fixed size packets, prior to multiplexing on the line. The synchronous line can carry these packets at a minimum rate of 4000 packet slots per second. In STDM each terminal is assigned a packet slot which recurs periodically. In contrast, for DM, packets are multiplexed on the line asynchronously into unoccupied packet slots. Alternative implementations of the DM technique were studied, one where each terminal transmits and receives at a maximum rate of 4000 packets per second and another where the maximum rate is 2000 packets per second. As part of its message handling function the Central Switch buffers messages in transit. This allows User Terminals to transmit and receive messages with a degree of independence from one another. However the terminal strategy affects the amount of storage required in the Central Switch. In order to prevent the loss of information when there is insufficient buffering there is a mechanism to inhibit traffic from User Terminals when the Central Switch's buffer is near overflow. Due to this control of traffic, there is a relationship between the amount of data that flows through the Switch and the amount of buffering in the Switch. Simulation results showed that there was little difference in delay performance between the two implementations of DM. However an analysis comparing DM and STDM showed a great difference in performance for all but the very heaviest line loadings. This difference increases as the number of terminals sharing the T1 line increases. Our study concentrated on two aspects of buffering in the Central Switch. We examined the relationship between throughput and the amount of storage available in the switch. The results of a simulation study showed that throughput can be quite high for all but minimal storage in the switch. Moreover, a strategy that dedicates buffers does quite well compared to common buffering. The second aspect of the study concentrated upon the User Terminal's strategy. Since each terminal acts independently, there may be strategies that make particularly high demands upon storage capacity in the Central Switch. An analysis showed that at the loadings where the system would be expected to operate, the user strategy in transmitting and receiving messages has little effect.