Parallel processing for block ciphers on a fault tolerant networked processor array
International Journal of High Performance Systems Architecture
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In the age of highly integrated system LSIs, designmethodologies for shorter time-to-market and higher re-programmabilityafter the chip fabrications are now key re-searchissues because of the difficulty of complete verifica-tionbefore tape-out of LSI designs. In this paper, we firstintroduce a IP-based VLSI architecture that consists of amain processor and an additional hardware (both customhard macros and FPGA on a single chip) specialized to bein charge of the specific instructions. We further replacethe controller circuits of the specialized hardware with compactmicro-controllers and memories by using IP libraries(hard macros), which results in the increase of the debuggabilityand the flexibility of design even for computationsrealized by hard macros. We call the proposed architectureas Field Modifiable Architecture (FMA). Experimental resultsconfirm that our architecture can achieve significantperformance improvement in terms of execution cycles andthat EC (Engineering Change) can be successfully accommodated"after" chip fabrications.