On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
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In this paper we propose an efficient method to observe a processor state machine and to detect illegal states within one clock-cycle. The strategy is based on a comparison of an encoded vector VCP1, representing the real state, and a predicted vector YCP2, representing the expected state. The practical applicability of the concept was evaluated on several experimental processor designs. We implemented check-units for 8-, I6- and 32-bit microprocessors and DSPs with sets of 32 up to 214 instructions and a deterministic control-flow. The applicability to processors with a higher complexity is demonstrated by a check unit for state machine on-line observation of a pipelined microprocessor with superscalar data-path and hardware-implemented hazard control. To minimize the overhead we investigated different strategies to modify check units. A reduction of hardware overhead can be reached by application specific reduction of processor state machines. For more complex processors we propose a reduction of the overhead by partitioning of the state space.