TED+: a data structure for microprocessor verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
A new, compact, canonical representation for arithmetic expressions, called Taylor Expansion Diagram, is presented. This representation is based on a non-binary decomposition principle. It treats the expression as a continuous, differentiable function and applies Taylor series expansion recursively over its symbolic variables. The resulting Taylor Expansion Diagram (TED) is canonical for a fixed variable order.We present a theory of TED, and show how to obtain a reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hardware implementations of arithmetic designs, and especially the equivalence checking of complex arithmetic expressions that arise in symbolic verification.