Formal Verification of the Pentium 4 Multiplier

Authors:
Roope Kaivola;Naren Narasimhan
Affiliations:
-;-
Venue:
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Year:
2001

Citing 0
Cited 2

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Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

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Abstract

We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium 4 microprocessor. The verification is based on a combination of theorem-proving and model-checking tasks performed in the Forte hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like Binary Moment Diagrams or its variants.