A Language Formalism for Verification of PowerPC(tm) Custom Memories Using Compositions of Abstract Specifications

  • Authors:
  • Jayanta Bhadra;Andrew Martin;Magdy Abadir;Jacob Abraham

  • Affiliations:
  • -;-;-;-

  • Venue:
  • HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
  • Year:
  • 2001

Quantified Score

Hi-index 0.00

Visualization

Abstract

We present a methodology in which the behavior of custom memories can be abstracted by a couple of artifacts { one for the interface and another for the contents. Memories consisting of several ports result into several user-provided abstract specifications, which in turn can be converted to simulation models. We show that (i) a simulation model is an approximation of the corresponding abstract specification and (ii) the abstracted memory core can be composed with the un- abstracted surrounding logic using a simple theory of composition. We make use of this methodology to verify equivalence between register transfer level and transistor level descriptions of custom memories.