Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal

Authors:
Wen-jann Yang;Ramalingam Sridhar;Victor Demjanenko
Affiliations:
-;-;-
Venue:
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Year:
1996

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Abstract

A parallel architecture is proposed for a high speed query server to process postal addresses with several fields. For a given component in a field, the offset addresses of records which contain the component in a postal address database are coded into a Compressed Bit Vector (CBV). Finding the appropriate CBV's and performing intersections to get matching offset addresses are key bottlenecks for the performance of the query server. These are implemented by a specialized hardware embedded in a general purpose computer for a cost effective solution. This hardware directly operates on the CBV's using parallel schemes. The architecture and algorithms for expanding a CBV, synchronizing the parallel processing of the processing units, and balancing the load in the pipelined stages are presented with simulation results.