Evaluating the performance of four snooping cache coherency protocols
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance evaluation of memory consistency models for shared-memory multiprocessors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
Comparative performance evaluation of cache-coherent NUMA and COMA architectures
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Evaluating the memory overhead required for COMA architectures
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Simple compiler algorithms to reduce ownership overhead in cache coherence protocols
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
COMA-F: a non-hierarchical cache only memory architecture
COMA-F: a non-hierarchical cache only memory architecture
Tolerating latency through software-controlled data prefetching
Tolerating latency through software-controlled data prefetching
Boosting the performance of hybrid snooping cache protocols
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
An assessment of COMA multiprocessors
IPPS '95 Proceedings of the 9th International Symposium on Parallel Processing
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Efficient management of memory hierarchies in embedded DRAM systems
ICS '99 Proceedings of the 13th international conference on Supercomputing
A Study of the Efficiency of Shared Attraction Memories in Cluster-Based COMA Multiprocessors
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
The Illinois Aggressive Coma Multiprocessor project (I-ACOMA)
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Virtual memory on data diffusion architectures
Parallel Computing
The diffusion space of data diffusion architectures
Parallel Computing
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A problem with bus-based shared-memory multiprocessors is that the shared bus rapidly becomes a bottleneck in the machine, effectively limiting the machine size to somewhere between ten and twenty processors. We propose a new architecture, the bus-based COMA (BB-COMA) that addresses this problem. Compared to the standard UMA architecture, the BE-COMA has lower requirements on bus bandwidth. We have used program-driven simulation to study the two architectures running applications from the SPLASH suite. We observed a traffic reduction of up to 70% for BB-COMA, with an average of 46%, for the programs studied. The results indicate that the BB-COMA is an interesting candidate architecture for future implementations of shared-bus multiprocessors.