Prefetching in supercomputer instruction caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Threaded prefetching: an adaptive instruction prefetch mechanism
Microprocessing and Microprogramming
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Machine Vision and Applications
A low power front-end for embedded processors using a block-aware instruction set
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
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A new lookahead instruction prefetching mechanism is proposed in this paper. Though significant performance improvement can be obtained by improving both the cache miss ratio and average access time for successfully prefetched blocks, most conventional prefetching mechanisms improve only one out of the two factors. To achieve balanced improvement of the two factors, a lookahead prefetching scheme that fetches multiple blocks for a prefetch request and adopts prefetch on miss mechanism is proposed. Performance evaluation is carried out through the trace-driven simulation and the proposed prefetch scheme reduces 32%/spl sim/56% of the memory access delay time of the cache system that does not perform any prefetching.