EXPLORER: an interactive floorplanner for design space exploration
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
GALLO: a genetic algorithm for floorplan area optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Hierarchical Parallel Genetic Algorithms using Grid computing
Future Generation Computer Systems
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A Multi-Selection-Multi-Evolution (MSME) scheme for parallelizing a genetic algorithm for floorplan optimization is presented and its implementation with MPI and its experimental results are discussed. Our experimental results on a 16 node IBM SP2 scaleable parallel computer have shown that the scheme is effective in improving performance of floorplanning over that of a sequential implementation. The parallel version could obtain better results with more than 90% of probability. Given 1000 second wall clock time, our parallel program could reduce both chip area and maximum path delay by more than 8% with 8 processors and 12% with 12 processors. Parallel computing can also speed up the evolution process so that there could be higher probability of obtaining a better solution within a given time interval.