Performance estimation in a simultaneous multithreading processor

Authors:
M. J. Serrano
Affiliations:
-
Venue:
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Year:
1996

Citing 3
Cited 0

State space exploration in Markov models

SIGMETRICS '92/PERFORMANCE '92 Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Performance tradeoffs in multistreamed superscalar architectures

Performance tradeoffs in multistreamed superscalar architectures
Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture

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Abstract

We present a model to estimate the performance of dynamically interleaving instruction streams in super-scalar architectures. Instructions executed per cycle (IPC) are calculated from simple descriptions of the workload and hardware. We compare estimates for several programs against results from a simulator.