T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
TAM—a compiler controlled threaded abstract machine
Journal of Parallel and Distributed Computing - Special issue on dataflow and multithreaded architectures
NORMA: a graph reduction processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
Overview of the Monsoon Project
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
THE MIT ALEWIFE MACHINE: A LARGE-SCALE DISTRIBUTED-MEMORY MULTIPROCESSOR
THE MIT ALEWIFE MACHINE: A LARGE-SCALE DISTRIBUTED-MEMORY MULTIPROCESSOR
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We present a case study of the use of a Unix/C/Verilog production environment to aid the design, from concept to physical prototype, of the PACE parallel graph rewriting architecture. The entire architecture has been modeled, so that simulated runs of complete programs are possible. The architecture's model is currently being refined towards a component by component detailed hardware design.