Minerva: An Adaptive Subblock Coherence Protocol for Improved SMP Performance
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
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The first commercially available CPU cache memory used a sector design, by which the cache consisted of sectors (address tags) and sub-sectors (or blocks, with valid bits). It rapidly became clear that superior performance could be obtained with the now familiar set-associative cache design. Because of changes in technology, the time has come to revisit the design of sector caches.Sector caches have the feature that large numbers of bytes can be controlled using relatively small numbers of tag bits, while not having to transfer very large blocks. This suggests the use of sector caches for multi-level cache designs. In such a design, the cache tags can be placed at a high level (e.g., on the processor chip) and the cache data array can be placed at a lower level (e.g., off-chip).In this paper, we present a thorough analysis of the design and use of uniprocessor sector caches. We start by creating a standard workload and then through simulation derive miss ratios for a wide range of sector cache designs. Those miss ratios are transformed into Design Target Miss Ratios, which are intended to be representative of a wide range of workloads. The miss ratios are then used to estimate performance, using typical timings, for a variety of one-level and two-level cache designs.We find that for single-level caches, sector caches are seldom advantageous. For multi-level cache designs with small amounts of storage at the first-level caches, as would be the case for small on-chip caches, sector caches can yield significant performance improvements. For multi-level designs with large amounts of first-level storage, sector caches provide relatively small improvements.