A cycle-accurate transaction level SystemC model for a serial communication bus
Computers and Electrical Engineering
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This paper describes a proposed modeling and designenvironment for teaching the concepts of performance modeling ofhardware/software systems to senior computer engineeringundergraduate students. This environment is being developed tosupport senior capstone design projects in computer engineering.Portions of this environment are currently being beta tested andeducational material, including lecture slides and laboratoryexercises, based on the use of the environment are being developed.