A high-speed parallel sensing scheme for multi-level non-volatile memories

Authors:
C. Calligaro;R. Gastaldi;A. Manstretta;G. Torelli
Affiliations:
-;-;-;-
Venue:
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Year:
1997

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Cited 1

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies

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Abstract

A parallel sensing scheme for multi-level non-volatile memories (ML NVM) is presented. A single comparison step is used to achieve high sensing speed. To this purpose, a high-speed low-voltage current comparator is used. Experimental evaluations on a 0.6-/spl mu/m EPROM test chip demonstrated the feasibility of 4-level-cell NV MLMs from the sensing standpoint. A read throughput of 12 MB/s is achieved with the proposed 4-level-cell memory architecture. Multi-level storage is achieved by using a program-verified scheme to obtain tight cell threshold voltage distribution. Overall sensing area overhead for a 32-Mbit chip is in the range of 1%.