Dynamic removal of redundant computations
ICS '99 Proceedings of the 13th international conference on Supercomputing
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Evaluating high-level language pointer-expressions can require a significant portion of the execution time and memory bandwidth in programs, especially for pointers with multiple memory accesses and address computations. Often such pointers repeatedly follow the same evaluation paths and return the same values. We present a microarchitecture technique that dynamically eliminates the execution of pointers based on results obtained from previous evaluations, without using prediction. We experiment with a benchmark set that includes continuous-speech recognition, MPEG-1 decoding, and SPECint95 ijpeg, li and go programs. Simulations of Digital Alpha 21164 microprocessor show that the eliminated pointers account for up to 11.3% of execution time, and 26% of data memory bandwidth of an entire program. Hence, the proposed microarchitecture provides substantial performance gains by significantly reducing the number of executed pointers.