Scalable and structured scheduling
International Journal of Parallel Programming
On control signals for multi-dimensional time
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Automatic generation of fpga-specific pipelined accelerators
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Synchronization-Free automatic parallelization: beyond affine iteration-space slicing
LCPC'09 Proceedings of the 22nd international conference on Languages and Compilers for Parallel Computing
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
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We study in this paper the problem of polyhedron scanning which appears for example when generating code for transformed loop nests in automatic parallelization. After a review of related works, we detail our method to scan affine images of polyhedra. After some experimental results we show how our method applies to unions of affine images of polyhedra.We have taken the option to generate low level code without loops. This has allowed us to have a completely general and fully parameterized method without losing efficiency.