The impact of delay on the design of branch predictors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
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A sequence of branch instructions in the dynamic instruction stream forms a branch sequence if at most one non-branch instruction separates each consecutive pair of branches in the sequence. We propose a branch prediction scheme in which branch sequence history is explicitly maintained to identify frequently encountered branch sequences at runtime and when the first branch in the sequence is encountered, the outcomes of the all of the branches in the sequence are predicted. We have designed an implementation of a branch sequence predictor which provides overall misprediction rates that are comparable with the gshare single branch predictor. Using this branch sequence predictor we have devised a new instruction fetch mechanism. By saving the instructions following the first branch belonging to a branch sequence in a sequence table, the proposed mechanism eliminates fetches of non-consecutive instruction cache lines containing these instructions and therefore delays associated with their fetching is avoided. Experiments comparing the proposed fetch mechanism with a simple fetch mechanism based upon a single branch prediction for Spec95 benchmarks demonstrate that the total number of I-cache lines fetched during execution decreases by as much as 15%, the number of useful instructions per fetched cache line increases by as much as 18%, and the overall IPCs achieved on a superscalar processor increase by as much as 17% for some benchmarks.