A novel network node architecture for high performance and function flexibility
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
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The Naval Research Lab (NRL) has developed a graphical notation called the Processing Graph Method (PGM) and a set of tools to implement the PGM environment called PGM Tools (PGMT). A major capability currently missing from PGMT is to receive feedback on the performance of the algorithm and scheduler on a specific architecture without actually executing the algorithm on that architecture with real data. The parallel computing architecture used in NRL is the i860 based Mercury RACE Multi-computer. The RACEway interconnection network is a hierarchical crossbar-based network which supports concurrent, priority-based, preemptable data transfer between system nodes. This paper outlines a performance modeling methodology based on the UVa ADEPT VHDL-based performance modeling environment. A simulation model for the RACEway crossbar interconnection network is presented to evaluate the performance of the network with respect to the traffic load on it. The integrated architecture/algorithm/scheduler model also provides an efficient way to evaluate the application algorithms and scheduling strategies on a specific multi-computer system.