Petri nets: an introduction
Performance models of multiprocessor systems
Performance models of multiprocessor systems
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Microcomputer Busses and Links
Microcomputer Busses and Links
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Application of Laplace Transform Techniques to the Analysis of Timed Petri Nets
International Workshop on Timed Petri Nets
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Performance Evaluation of Systems Using Nets
Proceedings of the Advanced Course on General Net Theory of Processes and Systems: Net Theory and Applications
On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
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The work addresses the design of hardware interface controllers for microprocessor-based systems. Interface design is required during the system integration phase to interconnect components which may use different interfacing protocols. It is shown that both the component interfacing protocols and the interface design can be described using an interpreted timed Petri net. Traditionally verification of the design is performed after the design has been synthesized. Such an approach usually requires several iterations, if the implementation violates some of the design constraints. A symbolic timing analysis is proposed to alleviate this problem: tight bounds on the interface path delays are computed using the available information from the protocol specifications prior to interface implementation. This is possible because our model can describe both circuit delays and environmental timing constraints. An example involving bus arbitration in the VMEbus is used to illustrate the analysis technique.