Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture

• Authors: I. Gracia;D. Gil;I. C. Baraza;P. J. Gil
• Venue: PRDC '02 Proceedings of the 2002 Pacific Rim International Symposium on Dependable Computing
• Year: 2002

As the use of dependable systems is generalising, theirstudy in early phases of the design cycle is more and moreimportant in order to save time and money. In this work,using a generic VHDL-based fault injection tool, called V FIT(VHDL-Based Fault Injection Tool), we have validated thedependability of a real Fault- Tolerant System using its VHDLmodel. The system studied is based on the Time- TriggeredArchitecture. It is a synchronous protocol with static schedulingthat has been specifically targeted at hard real-timefault-tolerant distributed system. The use of this system isgrowing in aircraft and automotive areas (x-by-wire). Wehave analysed the pathology of the propagated errors, measuredtheir latencies, and calculated both error detection latenciesand coverages. As the main conclusion of this work, wehave detected an erroneous implementation of the firmwareof the controller as well as results show that built-in selftestmechanisms detect the larger part of errors.