On the Representation of Timed Polyhedra
ICALP '00 Proceedings of the 27th International Colloquium on Automata, Languages and Programming
Symbolic Verification and Analysis of Discrete Timed Systems
Formal Methods in System Design
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In this paper, we suggest interval diagram techniques for formal verification of real-time systems modeled by means of timed automata. Interval diagram techniques are based on interval decision diagrams (IDDs) -- representing sets of system configurations of, e.g., timed automata -- and interval mapping diagrams (IMDs) -- modeling their transition behavior. IDDs are canonical representations of Boolean functions and allow for their efficient manipulation. Our approach is used for performing both timed reachability analysis and real-time symbolic model checking. We present the methods necessary for our approach and compare its results to another, similar verification technique -- achieving a speedup of 7 and more.