ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Cache performance of operating system and multiprogramming workloads
ACM Transactions on Computer Systems (TOCS)
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
IEEE Transactions on Computers
On the inclusion properties for multi-level cache hierarchies
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
Mache: no-loss trace compaction
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Efficient trace-driven simulation method for cache performance analysis
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Blocking: exploiting spatial locality for trace compaction
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Generation and analysis of very long address traces
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Sampling of Cache Congruence Classes
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Analysis of cache replacement-algorithms
Analysis of cache replacement-algorithms
Two Methods for the Efficient Analysis of Memory Address Trace Data
IEEE Transactions on Software Engineering
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We focus on the simulation techniques in order to reduce the space and time requirements for simulating large caches. First, we propose a space sampling technique to perform trace reduction for time and space. Our approach is to perform stratified sampling based on an index of locality. Our results show that the technique can provide accurate estimate of performance metric using only a small portion of trace references. Alternatively we also propose a time sampling approach, which performs sampling on loop iterations and requires that references between inter loop intervals be fully simulated. We show that the time sampling technique may give representative performance results for the entire loop execution. Depending on different workloads, the approach has been shown to be very effective in reducing simulation time at the cost of small estimate errors.