A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Scalable multiprocessors and the DASH approach (videotape)
Scalable multiprocessors and the DASH approach (videotape)
The DASH prototype: implementation and performance
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The design and analysis of DASH: a scalable directory-based multiprocessor
The design and analysis of DASH: a scalable directory-based multiprocessor
Simulation of the MC88000 Microprocessor System on a Transputer Network
EDMCC2 Proceedings of the 2nd Euronean Conference on Distributed Memory Computing
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An interactive environment for the teaching of computer architecture
ITiCSE '96 Proceedings of the 1st conference on Integrating technology into computer science education
Technical note: a hierarchical computer architecture design and simulation environment
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on Web-based modeling and simulation
IEEE Micro
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HASE is a Hierarchical computer Architecture design and Simulation Environment which allows for the rapid development and exploration of computer architectures at multiple levels of abstraction, encompassing both hardware and software. The user interacts with HASE via an X-Windows/Motif graphical interface, and one of the main forms of output is an animation of the design window. The DASH architecture was designed to prove the feasibility of building a scaleable high performance machine with multiple coherent caches and a single address space. The HASE simulation therefore concentrates on implementing the cache coherency protocols, and the animator has been used to check that the simulation conforms to the architecture. Future work will involve performance checks of the simulator, and thence possible architectural enhancements.