Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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The unpredictable variation in microelectronic circuits due to process tolerances increases significantly with increased levels of miniaturization. If ignored, the variation will result in poor manufacturing yield. If a worst-case approach is adopted, a loss of competitive edge results. This situation provides the motivation for efficient robust design of VLSI circuits. A method is proposed which generates a modular neural network MANN for mapping process level parameters to circuit performance. The MANN-an adaptive mixture of local experts competing to learn different aspects of a problem-is employed in performing extremely efficient optimization of the circuit yield at minimal cost. The MANN calculates circuit performance and optimizes yield with 97% accuracy at 20% of the cost of a full SPICE simulation.